`timescale 1ns / 1ps

module graycode(
    input rst_n_i,
    input clk_i,
    input en_i,
    output [3:0] gray_o
    );

    parameter [3:0] binary_max = 4'b1111;
    reg [3:0] binary = 4'b0;
    wire rst = ~rst_n_i;

    always@(posedge clk_i or posedge rst) begin
        if (rst == 1'b1) begin
            binary <= 4'b0;
        end else if (en_i) begin
            binary <= (binary>=binary_max) ? 4'b0 : binary+4'b1;
        end else begin
            binary <= binary;
        end
    end

    assign gray_o[3] = binary[3];
    assign gray_o[2] = binary[3] ^ binary[2];
    assign gray_o[1] = binary[2] ^ binary[1];
    assign gray_o[0] = binary[1] ^ binary[0];
endmodule
